1. Technical Field
The inventive concept relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of minimizing mismatch of transistors which operate in pairs in a sense amplifier.
2. Related Art
Semiconductor memory devices generally include bit line sense amplifiers which sense and amplify data stored in memory cells.
A method of sensing by a general sense amplifier is by differential pair sensing. The most commonly used sense amplifier is a cross-coupled latch type sense amplifier.
However, invalid sensing, or sensing of invalid data, may occur in cross-coupled latch type sense amplifier when there is mismatch of a threshold voltage between components (for example, transistors) of the sense amplifier.
FIG. 1 is a circuit diagram illustrating a configuration of a general cross-coupled latch type sense amplifier unit corresponding to a folded type bit line structure.
The sense amplifier unit 1 operates by power supply signals SAP and SAN. The sense amplifier unit 1 includes a sense amplifier 2, a precharge unit 4, an equalization unit 6, and a data output unit 8. The sense amplifier 2 senses and amplifies a difference between signals of a bit line pair BL and /BL. The precharge unit 4 is enabled by a precharge signal BLEQ when the sense amplifier 2 does not operate, and precharges the bit line pair BL and /BL to a bit line precharge voltage VBLP. The equalization unit 6 is enabled by the precharge signal BLEQ, and causes voltage levels of the bit line pair BL and /BL to be equalized. The data output unit 8 outputs a data signal amplified by the sense amplifier 2 through local data lines LDB and LDBB according to a column control signal Y1. FIG. 1 illustrates one example of the circuit configuration of the sense amplifier unit 1. In other implementations, a substantial configuration of the sense amplifier 1 may be varied according to a manufacturer or a specification of a memory device.
Among the configuration of the sense amplifier unit 1, the sense amplifier 2, the precharge unit 4, and the data output unit 8 operate by forming two transistors in pairs. Thus, when mismatch occurs between transistors that form one or more of the pairs, the semiconductor device does not normally operate.
FIG. 2 is a view illustrating a substantial layout of the sense amplifier unit 1 formed in a second-generation double data rate type three (2G DDR3) memory device having a 6F2 structure.
Referring to FIG. 2, transistors EQ TR of the equalization unit 6 are formed in a center portion of the sense amplifier unit 1. NMOS transistors Latch Tr-NMOS and PMOS transistors Latch Tr-PMOS constituting the sense amplifier 2 are formed at both sides of the equalization unit 6.
The NMOS transistors Latch Tr-NMOS and the PMOS transistors Latch Tr PMOS are formed so that two transistors form each pair and the transistor pairs are disposed in parallel. That is, in each sense amplifier 2, two NMOS transistors SAN(L) and SAN(R), in which drains thereof are commonly connected, and two PMOS transistors SAP(L) and SAP(R), in which drains thereof are commonly connected, form pairs and are disposed in parallel at both sides of the transistors EQ Tr of the equalization unit 6.
When the sense amplifier is manufactured, impurities are implanted into active regions of NMOS transistors in a state that PMOS transistor regions are covered by a photoresist PR with NMOS transistor regions being open.
In the NMOS transistors Top SAN(R) and Top SAN(L) and the NMOS transistors Bottom SAN(R) and Bottom SAN(L) that are arranged in parallel, distances of the active regions of the NMOS transistors Top SAN(R) and Top SAN(L) spaced from a sidewall PRW of the photoresist PR, which covers the PMOS transistor regions, are different. Distances of the active regions of the NMOS transistors Bottom SAN(R) and Bottom SAN(L) spaced from the sidewall PRW of the photoresist PR are different. Thus, a mismatch may result when concentrations of impurities implanted into the active regions are different in an impurity implantation process. That is, since the distances between the NMOS transistors Top SAN(R) and Top SAN(L) and the sidewall PRW of the photoresist PR and the distances between the NMOS transistors Bottom SAN(R) and Bottom SAN(L) and the sidewall PRW of the photoresist PR are different, impurities reflected from the sidewall of the photoresist PR in the impurity implantation process are mostly implanted into the NMOS transistors Top SAN(R) and Bottom SAN(L) adjacent to the sidewall PRW of the photoresist PR. Thus, mismatch occurs between the two NMOS transistors SAN(L) and SAN(R), which operate in pair. Similarly, mismatch also occurs between the two PMOS transistors SAP(L) and SAP(R), which operate in pair.